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RT9643
5 Channel ACPI Regulator with Step-Down DC/DC Controller
General Description
The RT9643 is a combo regulator which is compliant to ACPI specification for desktop/motherboard power management and system application. The part features one switch regulator for DDR memory VDDQ power; three linear regulators including 1.5Amp peak sourcing/sinking capability regulator for DDR VTT, a 1.2V ultra-low-dropout linear controller for chipset miscellaneous power, a 3.3VSB power with 1.25Amp peak current capability; and 2 dual power control including 5VDL, and 3.3VDL control for S3 and S5 system power. The part totally feature 5 sets power which are compliant to ACPI specification into a single small footprint package VQFN-24L 5x5. The part is generally operated to conform to ACPI specification, in S3 state, there are only VDDQ and 3.3VSB regulators remain on while the VTT and ULDO regulators are off. In the transition from S3 to S0, an external SS capacitor is attached for linear regulators to control its slew rates respectively to avoid inrush current induced. Moreover, the PGOOD signal raises high in S0 stage while all 3 regulators go stable. In the stage of S5 (EN = 0), there only 3.3VSB LDO remain on, while the other regulators are powered down. The VDDQ PWM regulator is a voltage mode implementation with external compensation to provide high load transient response. The VTT is regulated to follow 1/2 of VDDQ and is capable of sourcing or sinking 1.5A peak currents.
Features
Integrated 5 Channels Power Regulator DC/DC Buck PWM Regulator for VDDQ (2.5V or 1.8V) Linear Regulator Supports 1.5Amp Peak Sinking/ Sourcing Capability for VTT 1.2V Ultra-Low-Dropout Linear Controller for GMCH VTT Power 3.3VSB Linear Regulator Supports 1.25A Capability 5VDL Switch Control 3VDL Switch Control Conform to ACPI Specification Support Power Management at S0, S3, and S5 State 300kHz Fixed Frequency Switching RDS(ON) Current Sensing or Optional Current Sense Resistor for Precision Over-Current Detect Embedded Synchronous Boot-Strapped Diode Power Good Signal Indication for All Voltages Thermal Shutdown 24-Lead VQFN Package RoHS Compliant and 100% Lead (Pb)-Free
Applications
DDR VDDQ and VTT Voltage Generator with ACPI Support Desktop System Power Servers System Power
Ordering Information
RT9643 Package Type QV : VQFN-24L 5x5 (V-Type) Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard)
Pin Configurations
(TOP VIEW)
REF_IN COMP GND
19 18 17 16
24
23
22
21
1.2V_DRV 1.2V_FB 5VSB_DRV 5V_MAIN VTT_SNS VTT_OUT
ILIM
20
SS
FB
1 2 3 4 5 6 25
EN S3#I VCC_EN 3VSB_OUT VCC PGOOD
Note : Richtek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating. DS9643-03 August 2007
GND
15 14 13
7
8
9
10
11
12
BOOT
UGATE
ISNS
VDDQ_IN
VQFN-24L 5x5 www.richtek.com 1
PHASE
LGATE
RT9643
Typical Application Circuit
5V_MAIN 12V L2
R4
RT9643
Q3 5V DUAL Q4 5VSB 3.3 MAIN Q5 C12 3V DUAL R8 1.2 OUT C17 VDDQ 5VSB R7 Q6 C13 3 5VSB_DRV 4 16 VCC_EN 5V_MAIN UGATE 9 Q1 R3 Q2 R2 C2 C1
PHASE 10 ISNS LGATE GND 11 12 19, Exposed Pad (25) 8 23 22 C9 R6 C5
L1 V DDQ
>
17 S3#I 15 3VSB_OUT 2 1
C OUT
1.2V_FB 1.2V_DRV
BOOT FB COMP
R1 C6
C4
C3 R5
Chip Enable
14 VCC 21 SS 20 ILIM 13 PGOOD 18 EN
VDDQ_IN 7 VTT_SNS 5 REF_IN VTT_OUT 24 6 C8 C7
C11 C10
R9 R10
Operation
The RT9643 provides 5 functions: 1. A general purpose PWM regulator, used to generate VDDQ power for DDR memory. 2. A source-sink linear VTT regulator capable of sinking and sourcing 1.5A peak(minimum). 3. An adjustable Low Drop Out controller which, in conjunction with an external N-Channel power MOSFET, provides a programmable low voltage output. It normally provides 1.2V for GTL FSB termination voltage. 4. Generating a 5V DUAL voltage using an external N-channel to supply power from 5V MAIN in S0, and an external P-Channel to provide power from 5V Standby (5VSB) in S3. 5.An internal LDO which regulates "3V DUAL" in S3 mode from VCC(VSB). In S3, this regulator is capable of 1.25A peak currents with current limit protection (2A typ.). 100k pull up resistor to VOUT to obtain an output voltage. When the output voltage arrive 90% of normal value the power good will output voltage with 3ms delay time. When the output voltage falling arrive 75% of normal value the power good will turn off with less than 1ms delay time. But, there are two exceptions. One is the enable pull low the power good will turn off quickly. The second is the VCC falling arrive POR value (4V typ.) the power good also will turn off quickly.
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Table 1. While S5aS0aS3
State S5 S3 S0
S3#I X L H
EN(S5#) L H H
VCC_EN 5VSB_DRV L L H L L H
VDDQ OFF ON ON
VTT_OUT OFF OFF ON
1.2 OUT OFF OFF ON
3V Dual ON ON OFF
5V Dual OFF +5VSB +5VMAIN
Start up Sequencing The VCC pin provides power to all logic and analog control functions of the regulator including : After VCC is above UVLO, the start-up sequence begins as shown in Figure 1.
UVLO 5VSB ~4V 2.5V 1.5V SS 2.0V
3V Dual VDDQ VTT_OUT/ 1.2 OUT T0 T1 T2 T3 T4 T5 T6 T7 T8
Figure 1 T0 to T3 : After initial power-up, the IC will ignore all logic inputs for a time period (T3-T0) of about :
T3 - T0 =
6.5 x CSS 5
The 3V Dual LDO is in regulation. The 3.3V LDO' s slew rate is limited by the discharge slope of CSS. If 3V MAIN has come up prior to this time, the 3V DUAL node will already be pre-charged through the body diode of Q5 (see Figure 1). T3 to T4 : The IC waits about 100s before initiating soft-start on VDDQ to allow CSS time to fully discharged. The IC is in "SLEEP" or S5 state when EN is low. In S5 only the 3.3V LDO is on. If the IC is in S5 at T4, CSS will be held to 0V. T4 to T5 : While First time to enter S0, The IC will start VDDQ only if 5V_MAIN is above its UVLO threshold (5V_MAIN o.k.) and S3#I is high. T5 to T7 : After VDDQ is stabilized (when CSS is above about 1.5V) which will allow the 1.2V LDO and the VTT LDO to soft start. To ensure that the VDDQ output is not subjected to large transient currents during transition, the VTT and 1.2V LDO slew rates are limited by the slew rate of the CSS until the LDO is in regulation. In addition, the VTT regulator is current limited. T8 (S0 to S3) : Dropping the S3#I signal. When this occurs, VCC_EN goes low, and the 3.3V LDO turns on. The 1.2V LDO and the VTT LDO are turned off, and CSS is discharged to 2V. 5VSB_DRV pulls low to turn on the P-Channel 5V DUAL switch.
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S3 to S0 : The system signals this transition by raising the S3#I signal. S0 mode is not entered until 5V_MAIN o.k.. Then the following occurs : VCC_EN releases and pull high by external resistor. 5VSB_DRV pulls high to turn off the P-Channel switch. The 3.3V LDO turns off. The 1.2V LDO and the VTT LDO are turned on and CSS is allowed to charge up In most systems, the ATX power supply is enabled when S3#I goes to high. At that point, 5V_MAIN and 3.3 MAIN will start to rise. The RT9643 waits until 5V_MAIN is above 4.5V to turn on Q3 and Q5. This can cause about a 10% "bump" in both 5V DUAL and 3.3V DUAL when Q3 and Q5 turn on, since at that point, 5V_MAIN and 3.3 MAIN are at 90% of their regulation value.
5V Dual 4.4V
5V_MAIN VCC_EN S3#I
Figure 2. S3 to S0 Transition (5V DUAL) To eliminate the "bump" add delay to the 5V_MAIN pin as shown below. The 5V_MAIN pin on the RT9643 does not supply power to the IC, it is only used to monitor the voltage level of the 5V_MAIN supply.
5V_MAIN to RT9643 5V_MAIN from ATX
Figure 3. Adding Delay to 5V_MAIN Another method to eliminate the potential for this "bump" is to use the PWR_OK to drive the 5V_MAIN pin. Some systems cannot tolerate the long delay for PWR_OK (>100ms) to assert, hence the solution in figure C may be preferable. S5 to S3 : During S5 to S3 transition, the IC will pull 5VSB_DRV low with 500nA current sink to limit inrush in Q4 if 5V MAIN is below its UVLO threshold. At that time, 5V Dual is charged. The limited gate drive controls the inrush current through Q4 as it charges C1 (Capacitance on 5V Dual). Depending on the CGD of Q4, the current available from 5VSB, and the size of C1, C13 may be omitted. IQ4(INRUSH) = C1 x 5 x 10 -7 C13 + C GD(Q4)
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Table 3. B.O.M of the Application Circuit
Component Description See notes below See notes below Capacitor 1uF, 10%, 16VDC, X7R, 0603 Capacitor 10nF, 10%, 50VDC, X7R, 0603 Capacitor 10nF, 10%, 16V, X7R, 0603 Capacitor 220pF, 10%, 50VDC, NPO, 0603 Capacitor 10nF, 10%, 50VDC, X7R, 0603 Capacitor 220nF,10%, 10VDC, X7R, 0603 Capacitor 100nF, 10%, 25VDC, X7R, 0603 Inductor 1.8uH, 3.24m?16 Amps , Inductor 0.39uH, 2.8m, 15 Amps MOSFET N-CH, 8.8m, 30V, 50A, D-PAK, FSID: FDD6296 MOSFET N-CH, 6m, 30V, 75A, D-PAK, FSID: FDD6606 MOSFET N-CH, 32m, 20V, 21A, D-PAK, FSID: FDD6530A MOSFET P-CH, 35m, -20V, -5.5A, SSOT-6, FSID : DC602P Resistor 1.82k, 1%, 0805 Resistor 56k, 1%, 0805 Resistor 11.8k, 1%, 0805 Resistor 3.01k, 1%, 0603 Resistor 9.09k, 1%, 0603 Resistor 10k, 1%, 0805 Resistor 1k, 1%, 0805 RT9643 2 1 1 1 2 1 1 1 1 1 1 3 1 4 1 1 1 1 1 1 1 Qty Ref Cout C1,C12,C17 C2,C4 C3 C6 C9 C10, C11 C5 C8 L1 L2 Q1 Q2 Q3,Q5,Q6 Q4 R1,R2,R9,R10 R5 R6 R7 R8 R4 R3 U1 TDK TDK WALSIN WALSIN TDK WALSIN WALSIN Inter-Technical Inter-Technical Fairchild Fairchild Fairchild Fairchild Yageo Any Any Any Any Any Any RichTek Vendor
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Function Block Diagram
S3#I VCC_EN 5VSB_DRV EN 5V_MAIN VCC BOOT
VTT_SNS FB FB1.2
UVL
UV
VR Gate Control VDD
UGATE PHASE LGATE GND ISNS COMP
PGOOD
PGOOD
Soft-Start and Control Circuit
+ +
OC
+ + +
1.2V_DRV 1.2V_FB VCC
RA
FB VDDQ_IN
+
+
Oscillator
+
VTT_OT
3VSB_OUT
SS
ILIM
REF_IN
VTT_SNS
Functional Pin Description
1.2V_DRV (Pin1) Gate drive for 1.2V linear controller. The pin will be turned off (low) in S3 and S5 state. 1.2V_FB (Pin2) Feedback for the 1.2V linear controller. The pin is applied for 1.2V LDO output regulation sense. The voltage can be disabled by pulling the pin higher than 0.9V. 5VSB_DRV (Pin3) 5VSB Control Switch. The pin is applied to drive an external P-Channel MOSFET to switch 5VDL power to 5VSB in S3 stage. The pin goes high in S0 and S5. 5V_Main (Pin4) 5V main power. When this pin is below 4.5V, transition from S3 to S0 is inhibited. UGATE (Pin9) High-Side Drive. High-side MOSFET driver output of VDDQ PWM. Connect to gate of high-side MOSFET.
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VTT_SNS (Pin5) Remote sense for VTT. The pin is applied to remote sense the output voltage of VTT. VTT_OUT (Pin6) Output of VTT. Regulator power VTT output. VDDQ_IN (Pin7) Input of external VDDQ. Input power of VTT, the VTT is implemented to tracking 1/2 VDDQ. BOOT (Pin8) PWM Boot. The pin is applied for VDDQ PWM bootstrapped power for the embedded driver power.
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PHASE (Pin10) Phase node of VDDQ PWM. The pin is applied to sense phase node of VDDQ PWM for gates switch control. ISNS (Pin11) Current Sense input. Monitors the voltage drop across the low-side MOSFET or external sense resistor for over current control. LGATE (Pin12) Low-Side Drive. The low-side MOSFET driver output. Connect to gate of low-side MOSFET. PGOOD (Pin13) Power Good Indication Signal. An open-drain output signal that will pull LOW if FB is outside of a 10% range of the 0.9V reference and the LDO outputs are > 80% or < 110% of its reference. PGOOD goes low when S3 is high. The power good signal from the PWM regulator enables the VTT regulator and the LDO controller. VCC (Pin14) IC VCC. 5VSB is generally applied for bias power for IC logics and gate driver control. The IC stays at standby until this pin is higher than 4.35V. 3VSB_OUT (Pin15) 3.3VSB LDO Output. Internal linear regulator and is capable to drive up to 1.25Amp peak current. The power is Turned off in S0 state, and on in S5 or S3 stage. VCC_EN (Pin16) VCC enable signal for dual power. The pin is applied to control VCC power on for 3.3VDL and 5VDL, the signal is an open drain output which pulls the gate of an two NChannel blocking MOSFETs low in S5 and S3. This pin goes high (open) in S0. S3#I (Pin17) S3 Input. When LOW, the VTT and 1.2V LDO regulators are turned off and 3.3VSB regulator is turned on the. PGOOD is set to low when S3#I is LOW. REF_IN (Pin24) VTT voltage setting. The VTT regulator tracks the voltage set the pin, typically, it should be 1/2VDDQ FB (Pin23) VDDQ PWM Feedback. The output feedback of VDDQ PWM. The pin is applied for voltage regulation, PGOOD, under-voltage, and over-voltage protection and monitoring. COMP (Pin22) Compensation pin of VDDQ PWM. Output of the PWM error amplifier. Connect compensation network between this pin and FB. SS (Pin21) Soft Start. A external capacitor is attached to control the slew rate of the converter during initialization as well as sets the initial slew rate of the LDO controllers when transitioning from S3 to S0. This pin is charged/discharged with a internal 5uA current source during initialization, and charged with 50uA during PWM soft-start. ILIM (Pin20) Current Limit setting pin. A external resistor is attached to set the current limit value. GND [Pin19, Exposed Pad (25)] IC GROUND. The ground power for whole chip. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. EN (Pin18) Chip ENABLE. Typically tied to S5#. When this pin is low, the IC is operated in standby mode, all regulators are off and VCC_EN is low.
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Absolute Maximum Ratings
(Note 1) Supply Input Voltage, VCC ------------------------------------------------------------------------------- 6.5V PHASE Voltage -------------------------------------------------------------------------------------------- GND - 5V to 24V UGATE Voltage -------------------------------------------------------------------------------------------- VPHASE - 0.3V to VBOOT + 0.3V LGATE Voltage --------------------------------------------------------------------------------------------- GND - 0.3V to VCC + 0.3V BOOT to GND ---------------------------------------------------------------------------------------------- 24V VCC_EN to GND ------------------------------------------------------------------------------------------- 24V BOOT to PHASE ------------------------------------------------------------------------------------------ 6.5V BOOT to UGATE ------------------------------------------------------------------------------------------ 6.5V UGATE to PHASE ---------------------------------------------------------------------------------------- 6.5V Input, Output or I/O Voltage ----------------------------------------------------------------------------- GND - 0.3V to VCC + 0.3V Storage Temperature Range ---------------------------------------------------------------------------- -65C to 150C Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------- 260C Junction Temperature Range ---------------------------------------------------------------------------- -20C to 125C Power Dissipation, PD @ TA = 25C VQFN-24L 5x5 --------------------------------------------------------------------------------------------- 1.923W Package Thermal Resistance (Note 4) VQFN-24L 5x5, JA ---------------------------------------------------------------------------------------- 52C/W ESD Susceptibility (Note 2) HBM (Human Body Mode) ------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 3)
Supply Voltage, VCC -------------------------------------------------------------------------------------- 5V 10% Ambient Temperature Range ---------------------------------------------------------------------------- -10C to 85C
Electrical Characteristics
(Rocommended Operating Conditions, unless otherwise specification)
Parameter Converter & POR
Symbol
Test Condition LGATE, UGATE open, FB > 0.9, I(VTT) = 0, EN = 1, S3#I = 1 EN = 1, S3#I=LOW, I(3.3)< 10mA EN = 0, I(3.3) = 0 Rising VCC
Min
Typ
Max
Units
---4.0 3.9 -4.3 3.9 --
6 6 2 4.2 4.05 150 4.4 4.1 300
24 24 4 4.4 4.2 -4.6 4.2 --
mA mA mA V V mV V V mV
VCC Current
IVCC
VCC UVLO Threshold
Falling Hysteresis Rising
5V_MainUVLO Threshold
Falling Hysteresis
To be continued
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Parameter Oscillator Frequency Ramp Amplitude pk-pk Ramp offset Reference and Soft Start Internal Reference voltage Soft Start Current SS discharge on resistance PWM Converter Load Regulation FB Bias Current Under Voltage shutdown Isns over-current threshold Over voltage threshold PWM Output Driver UGATE Output Resistance LGATE Output Resistance Sourcing Sinking Sourcing Sinking ---1.8 1.8 1.8 1.2 3 3 3 2 2us noise filter RILIM IOUT from 0 to 16A -2 0.75 65 145 110 -1 75 170 115 +2 1.25 80 195 120 % A % A % Initial ramp after power-up During PWM/LOD soft start EN = 0 0.891 ---0.900 5 48 280 0.909 ---V A A FOSC 250 --300 1.8 0.5 350 --kHz V V Symbol Test Condition Min Typ Max Units
PGOOD (Power good Output) and control pins, VDDQ output Lower threshold Upper threshold PGOOD Output Low Leakage Current VTT Regulator VDDQ IN Current VREF IN to VTT Differential Output Voltage Internal Divider Gain VTT Current Limit VTT Leakage Current VTT SNS input resistance VTT PGOOD Drop-Out Voltage S0 mode, IVTT = 0 IVTT = 0, TA = 25C IVTT = 1.25A (pulsed) EN=0 Pulse(300ms MAX), TA = 25C S3#I = Low VTT = 0.9V Measured at VTT SNS ITT = 1.5A --20 -40 0.493 1.5 -20 -80 -0.8 35 --0.498 3 -110 --70 20 40 0.503 4 20 -110 0.8 mA mV mV V/V A A k % V 2us noise filter 2us noise filter IPGOOD Pull up to 5V 86 108 ------92 115 0.5 1 % % V A
To be continued
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Parameter 1.2V LDO Regulation Drop-Out Voltage External Gate Drive Gate Drive Source Current Gate Drive Sink Current FB 1.2V PGOOD Threshold 3.3V LDO Regulation Drop-Out Voltage Control Function S3#I, EN input threshold S3#I, EN input Current Over-Temperature Shutdown Over-Temperature Hysteresis VCC_EN Output Low RDS(ON) VCC_EN Output High Leakage 5VSB_DRV Output Low resistance 5VSB_DRV Sink Current 5VSB_DRVOutput High 1 -1 ---VVCC_EN = 12V 5V_MAIN OK 5V_MAIN < UVLO ----1.25 -150 25 170 4 125 500 820 1.55 1 --300 10 200 -1200 V A C C A nA I(3.3) from 0 to 1.25A, VCC > 4.75V I(3.3) 1.25A 3.2 -3.3 -3.4 1.5 V V I(1.2) from 0 to 5A I(1.2) 5A, RDS(ON) < 50m VCC = 4.75V 1.17 -----1.2 --1.2 1.2 -1.23 0.3 4.5 --0.8 V V V mA mA V Symbol Test Condition Min Typ Max Units
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution is highly recommended. Note 3. The operating conditions beyond the recommended range is not guaranteed. Note 4. JA is measured in the natural convection at TA = 25C on a low effective thermal conductivity test board (single-layer, 1S) of JEDEC 51-3 thermal measurement standard.
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Application Information
PWM Regulator
The RT9643 combines a single-phase synchronous buck PWM controller designed to drive two N-Channel MOSFETs. It provides a highly accurate, programmable output voltage precisely regulated to low voltage requirement with an internal 0.9V reference. Setting the output voltage The output voltage of the PWM regulator can be set in the range of 0.9V to 90% of its power input by an external resistor divider. The internal reference is 0.9V. The output is divided down by an external voltage divider to the FB pin (for example, R1 and R2 in Typical Application Circuit). There is also a 1A precision (5%) current sourced out of FB to ensure that if the pin is open, VDDQ will remain low. The output voltage therefore is : 0.9V VOUT - 0.9V = + 1A R2 R1 To minimize noise pickup on this node, keep the resistor to GND (R2) below 2k. We selected R2 at 1.82k and solved for R1.
ILIM det.
source. The output voltage starts to go up when VCSS is larger than 0.4V. To prevent large duty cycles and high currents during the beginning of the PWM soft-start, Once CSS has charged to 1.3V, the output voltage will be in regulation. 1.3 x CSS The time it takes SS to reach 1.3V is : T1.3 = 50 where T1.3 is in ms if CSS is in nF. The PWM regulator' s latched faults are enabled until CSS charges up to 1.5V. When CSS reaches 2.5V, the VTT and 1.2V LDO will begin their soft-start ramps. After the VTT and 1.2V LDO regulators are in regulation, PGOOD is then allowed to go HIGH (open). UVLO on VCC will discharge SS and reset the IC. Current Sensing Section
ISNS RSENSE Current Sense + 2.5V ILIM x 10 ILIM Mirror 0.9V ILIM RILIM PGND
R1 =
R2 x (VOUT - 0.9) = 1.816k 1.82k 0.9 - 1A x R2
Figure 4. Current Sense & Limit The following discussion refers to Figure 4. The current through RSENSE resistor (ISNS) is sensed shortly after low side MOSFET is turned on. Setting the Current Limit An ISNS is compared to the current established when a 0.9 V internal reference drives the ILIM pin. RILIM, the RDS(ON) of Q2, and RSENSE determine the current limit :
The synchronous buck converter is optimized for 5V operation. Oscillator The internal oscillator frequency is 300kHz. The internal PWM ramp is reset on the rising clock edge. PWM Soft Start When the PWM regulator is enabled the circuit will wait until the VDDQ_IN pin is below 100mV to ensure that the soft-start cycle does not begin with a large residual voltage on the PWM regulator output. When the PWM regulator is disabled, 50 is turned on from VDDQ_IN to PGND to discharge the output. The voltage at the positive input of the error amplifier is limited to VCSS which is charged with a 50A current
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RILIM =
10 x 0.9 RSENSE x ILIMIT RDS(ON)
Where ILIMIT is the peak inductor current. Since the tolerance on the current limit is largely dependent on the ratio of the external resistors it is fairly accurate if the voltage drop on the Switching Node side of RSENSE is an accurate representation of the load current.
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When using the MOSFET as the sensing element, the variation of RDS(ON) causes proportional variation in the ISNS. This value not only varies from device to device, but also has a typical junction temperature coefficient of about 0.4%/C (consult the MOSFET datasheet for actual values), so the actual current limit set point will decrease proportional to increasing MOSFET die temperature. A factor of 1.6 in the current limit set point should compensate for all MOSFET R DS(ON) variations, assuming the MOSFET' s heat sinking will keep its operating die temperature below 125C. Current limit (ILIMIT) should be set sufficiently high as to allow inductor current to rise in response to an output load transient. Typically, a factor of 1.3 is sufficient. In addition, since ILIMIT is a peak current cut-off value, we will need to multiply ILOAD(MAX) by the inductor ripple current (20% is chosen). ILIMIT > ILOAD(MAX) x 1.6 x 1.3 x 1.2
REF
Frequency Loop Compensation The loop is compensated using a feedback network around the error amplifier, which is a voltage output OP Amp. Figure 5 shows a complete type3 compensation network. A type2 compensation configuration eliminates R3 and C3 and is shown in typical application circuit. Type2 compensation can be used for most applications. For critical applications that require wide loop-bandwidth, and use very low ESR output capacitors, type3 compensation may be required.
C1 C2 COMP
EA +
R2
ZFB
C3 R1
R3
ZIN VOUT
FB
Gate Driver Section The adaptive gate control logic translates the internal PWM control signal into the MOSFET gate drive signals providing necessary amplification, level shifting and shoot-through protection. Also, it has functions that help optimize the IC performance over a wide range of operating conditions. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate to source voltages of both upper and lower MOSFETs. The lower MOSFET drive is not turned on until the PHASE has decreased to less than approximately one VT (~0.6volt). Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately one VT (~0.6 volt). This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction, or shoot-through. There must be a low-resistance, low-inductance path between the driver pin and the MOSFET gate for the adaptive dead-time circuit to work properly. Any delay along that path will subtract from the delay generated by the adaptive dead-time circuit and shoot-through may occur. Figure 5. Compensation Network PGOOD Signal PGOOD monitors the status of the PWM output as well as the VTT and 1.2V LDO regulators. PGOOD remains low unless all of the conditions below are met : 1. S3#I is HIGH 2. SS is above 4V 3. Fault latch is cleared 4. FB is between 90% and 110% of VREF 5. VTT and 1.2V LDO regulators are in regulation Protection The converter output is monitored and protected against extreme overload, short circuit, over-voltage and undervoltage conditions. An internal "Fault Latch" is set for any fault intended to shut down the IC. When the "Fault Latch" is set, the IC will discharge VDDQ_IN by driving L GATE high until VDDQ_IN < 0.5V. LGATE will then go low until VDDQ_IN > 0.8V. This behavior will discharge the output without causing undershoot (negative output voltage).
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To discharge the output capacitors, a 50 load resistor is switched in from VDDQ_IN to PGND whenever the IC is in fault condition, or when EN is low. After a latched fault, operation can be restored by recycling power or by toggling the EN pin. Under-Voltage Shutdown If FB stays below the under-voltage threshold for 2s, the "Fault latch" is set. This fault is prevented from setting the fault latch during PWM soft-start (SS < 1.5V). Over-Current Sensing If the circuit' s current limit signal ("ILIM det" as shown in Figure 4) is high at the beginning of a clock cycle, a pulse skipping circuit is activated and UGATE is inhibited. The circuit continues to pulse skip in this manner for the next 8 clock cycles. If at any time from the 9th to the 16th clock cycle, the "ILIM det" is again reached, the fault latch is set. If "ILIM det" does not occur between cycle 9 and 16, normal operation is restored and the over-current circuit resets itself. This fault is prevented from setting the fault latch during soft-start (SS < 1.5V). 1. VDDQ_IN (PWM output voltage) > 1V and 2. FB < 100mV Any of these 3 faults will set the fault latch. These 3 faults can set the fault latch during the SS time (SS < 1.5V). To ensure that FB pin open will not cause a destructive condition, a 1A current source ensures that the FB pin will be high if open. This will cause the regulator to keep the output low, and eventually result in an Under-voltage fault shutdown (after PWM SS complete). Over-Temperature Protection RT9643 incorporates an internal over temperature circuit designed to protect the device during overload conditions. If the junction temperature reaches a nominal temperature of 150C, the over temperature circuit will shut the chip. Normal operation is restored at when the die temperature falls below 125C with internal Power On Reset asserted, resulting in a full soft-start cycle. To accomplish this, the over temperature comparator should discharge the SS pin. VTT Regulator The VTT regulator is a simple and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system. The regulator is capable of actively sinking or sourcing up to 1.25A while regulating an output voltage to within 40mV. The output termination voltage can be tightly regulated to track 1/2VDDQ_IN by two internal voltage divider resistors (50k for each resistor) or two external voltage divider resistors from the output of the PWM regulator. The VTT regulator also incorporates a high-speed differential amplifier to provide ultra-fast response in line/ load transient. Other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions. The VTT regulator is enabled when S3#I is HIGH and the PWM regulator's internal PGOOD signal is true. The VTT regulator also includes its own PGOOD signal which is high when VTT_SNS > 90% of REF_IN. LDO Controller The LDO controller combined with an external N-Channel MOSFET pass element is used to provide 1.2V for the
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PGOOD (5V/Div)
IL (10A/Div)
UGATE (10V/Div) LGATE (5V/Div)
Time (10s/Div)
Figure 6. Over Current Protection Waveform OVP / HS Fault / FB short to GND detection: A HS Fault is detected when there is more than 0.5V from PHASE to PGND 350ns after LGATE reaches 4V (same time as the current sampling time). OVP Fault Detection occurs if FB > 115% VREF for 16 clock cycles. During soft-start, the output voltage could potentially "run away" if either the FB pin is shorted to GND or R1 is open. This fault will be detected if the following condition persists for more than 14s during soft-start.
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RT9643
Front-side bus GTL termination. The driving voltage on the gate drive pin can be pull up to within 0.5V of VCC. Use low Vth MOSFET to assure RDS(ON) is small enough for full load operation. The soft start for the LDO is accomplished by clamping the input voltage to a smooth up-going ramp. The final input reference voltage after soft start is 0.9V. Component Selection Components should be appropriately selected to ensure stable operation, fast transient response, high efficiency, minimum BOM cost and maximum reliability. Output Inductor Selection The selection of output inductor is based on the considerations of efficiency, output power and operating frequency. For a synchronous buck converter, the ripple current of inductor (IL) can be calculated as follows : IL = (VIN - VOUT) x VOUT VIN x fOSC x L current from the input capacitor during the on time of upper MOSFET. The RMS value of ripple current flowing through the input capacitor is described as :
IIN(RMS) = IOUT x D x (1 - D)
The input bulk capacitor must be cable of handling this ripple current. Sometime, for higher efficiency the low ESR capacitor is necessarily. Appropriate high frequency ceramic capacitors physically near the MOSFETs effectively reduce the switching voltage spikes. MOSFET Selection The selection of MOSFETs is based upon the considerations of RDS(ON), gate driving requirements, and thermal management requirements. The power loss of upper MOSFET consists of conduction loss and switching loss and is expressed as : PUPPER = PCOND _UPPER + PSW_UPPER = IOUT x RDS(ON) x D + 1 IOUT x VIN x (TRISE + TFALL ) x fOSC 2
Generally, an inductor that limits the ripple current between 20% and 50% of output current is appropriate. Make sure that the output inductor could handle the maximum output current and would not saturate over the operation temperature range. Output Capacitor Selection The output capacitors determine the output ripple voltage (VOUT) and the initial voltage drop after a high slew-rate load transient. The selection of output capacitor depends on the output ripple requirement. The output ripple voltage is described as follows : VOUT 1 VOUT = IL x ESR + x 2 (1 - D) 8 fOSC x L x C OUT For electrolytic capacitor application, typically 90~95% of the output voltage ripple is contributed by the ESR of output capacitors. Paralleling lower ESR ceramic capacitor with the bulk capacitors could dramatically reduce the equivalent ESR and consequently the ripple voltage. Input Capacitor Selection Use mixed types of input bypass capacitors to control the input voltage ripple and switching voltage spike across the MOSFETs. The buck converter draws pulsewise
where TRISE and TFALL are rising and falling time of VDS of upper MOSFET respectively. RDS(ON) and QG should be simultaneously considered to minimize power loss of upper MOSFET. The power loss of lower MOSFET consists of conduction loss, reverse recovery loss of body diode, and conduction loss of body diode and is express as :
PLOWER = PCOND _LOWER + PRR + PDIODE = IOUT x RDS(ON) x (1 - D) + QRR x VIN x fOSC + 1 x IOUT x VF x TDIODE x fOSC 2
where TDIODE is the conducting time of lower body diode. Special control scheme is adopted to minimize body diode conducting time. As a result, the RDS(ON) loss dominates the power loss of lower MOSFET. Use MOSFET with adequate RDS(ON) to minimize power loss and satisfy thermal requirements. Bypass Capacitor Notes Input capacitor C1 is typically chosen based on the ripple current requirements. COUT is typically selected based on both current ripple rating and ESR requirement. C17
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RT9643
and C12 selection will be largely determined by ESR and load transient response requirements. PWM Layout Considerations MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency and radiate noise, that results in over-voltage stress on devices. Careful component placement layout and printed circuit design can minimize the voltage spikes induced in the converter. Consider, as an example, the turn-off transition of the upper MOSFET prior to turn-off, the upper MOSFET was carrying the full load current. During turn-off, current stops flowing in the upper MOSFET and is picked up by the low side MOSFET or schottky diode. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selections, layout of the critical components, and use shorter and wider PCB traces help in minimizing the magnitude of voltage spikes. There are two sets of critical components in a DC-DC converter using the RT9643. The switching power components are most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bypass current. The power components and the PWM controller should be placed firstly. Place the input capacitors, especially the high-frequency ceramic decoupling capacitors, close to the power switches. Place the output inductor and output capacitors between the MOSFETs and the load. Also locate the PWM controller near by MOSFETs. A multi-layer printed circuit board is recommended. Figure 9 shows the connections of the critical components in the converter. Note that the capacitors CIN and COUT each of them represents numerous physical capacitors. Use a dedicated grounding plane and use vias to ground all critical components to this layer. Apply another solid layer as a power plane and cut this plane into smaller islands of common voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the PHASE node, but it is not necessary to oversize this particular island. Since the PHASE node is subjected to very high dV/dt voltages, the stray capacitance formed between these island and the surrounding circuitry will tend to couple switching noise. Use the remaining printed circuit layers for small signal routing. The PCB traces between the PWM controller and the gate of MOSFET and also the traces connecting source of MOSFETs should be sized to carry 2A peak currents. Below PCB gerber files are our test board for your reference :
Figure 7. Component Side
Figure 8. GND
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RT9643
Figure 9. Power
Figure 10. Bottom
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DS9643-03 August 2007
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Outline Dimension
D
D2
SEE DETAIL A L 1
E
E2
e A A3 A1
b
1 2
1 2
DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.
Symbol A A1 A3 b D D2 E E2 e L
Dimensions In Millimeters Min 0.800 0.000 0.175 0.250 4.950 3.100 4.950 3.100 0.650 0.350 0.450 Max 1.000 0.050 0.250 0.350 5.050 3.400 5.050 3.400
Dimensions In Inches Min 0.031 0.000 0.007 0.010 0.195 0.122 0.195 0.122 0.026 0.014 0.018 Max 0.039 0.002 0.010 0.014 0.199 0.134 0.199 0.134
V-Type 24L QFN 5x5 Package
Richtek Technology Corporation
Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
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